Thermo-compression bonding (TCB) of solder capped micro bumps is the industry standard for high bandwidth memory (HBM) packaging. However, the assembly complexity and high cost has limited its high-volume adoption. Direct Bond Interconnect technology is an attractive alternate solution due to the instantaneous bond at room temperature. Two dielectric surfaces are bonded at room temperature, while the metal interconnection (Cu to Cu in most applications) is completed during a subsequent low temperature anneal (1500C – 3000C). The initial dielectric bonding process is performed at ambient temperature and pressure with no adhesive or other filler materials. Bonding takes place instantaneously once the two surfaces are brought into contact. Batch anneal is carried out in a conventional oven. Compared to thermal compression bonding, it has advantages of higher throughput and yield which drive the overall bonding costs down. 

Leading-edge technology integration, high-bandwidth and low-power data access call for vertical stacking of semiconductor devices with very fine pitch interconnects. To address this demand, a unique technology referred to as Direct Bond Interconnect (DBI®) which was invented by Ziptronix [1] is being further developed for die to wafer applications. 

Slide deck featuring DBI as an alternative to Thermal Compression Bonding

This paper presents Invensas' silicon interposer technology for heterogeneous chip integration. Various process module and integrated blocks were optimized for yield and high performance in the interposer. The modules under evaluation include TSV etch, barrier deposition, electrochemical plating, chemical mechanical polishing (CMP), temporary bonding, low temperature oxide (LTO) and low temperature polyimide (LTPI) passivation.

Bond Via Array (BVA) technology has been developed to enable more than 1000 vertical connections between memory and processor components in a standard outline Package-on-Package (PoP) configuration. This higher density interconnect more than doubles current PoP capability and thereby addresses next generation wide IO mobile device demands for increased bandwidth [1]-[3]. In this paper, we discuss BVA manufacturing process details and associated demonstration test vehicle design.

For 2.5D and 3D IC packaging, wafer back side processing often has temperature limits substantially lower than curing temperature of conventional polyimide (PI). New low temperature curable insulation materials possess very different properties and require thorough evaluation to ensure process compatibility and product reliability.