Scalability challenges in solder-based interconnects at <35 µm pitch has fueled the adoption of hybrid bonding technology. The Direct Bond Interconnect (DBI®) technology, which was developed originally for wafer-to-wafer (W2W) applications, has been extended to die-to-wafer (D2W) as DBI® Ultra. In this paper, we discuss test results for a new die-to-wafer hybrid bonding test vehicle with an interconnect design of 2 µm pad on 4 µm pitch.

The DBI® Ultra hybrid bonding technology is now ready for industry adoption and ramp to manufacturing. The value of the hybrid bonded Cu-Cu technology may be realized at various interconnect pitches for different applications. In this paper, we report on 5-die stack hybrid bonded module with TSV and the latest fabrication, assembly process, electrical testing, and reliability performance.

Wafer-to-wafer (W2W) direct bond interconnect technology has been in high-volume manufacturing for several years. We have been reporting development for extending this technology from wafer-to-wafer (W2W) to die-to-wafer (D2W) and die-to-die (D2D) applications over the past few years. In this paper, we assess the high-volume readiness of the technology using a die-to-wafer and die-to-die stacking. Critical enabling factors include the CMP process for bonding surface planarization and Cu recess control, metrology tools for CMP process control and verification, and compatibility with the silicon supply chain for assembly. Other important factors include the singulation technology and die handling.

Die-to-wafer or wafer-to-wafer direct bonding has been drawing significant attention and undergoing rapid development for its various applications in three-dimensional integrated circuits (3D-IC), such as image sensors, micro-electro-mechanical system (MEMS) sensors, and stacked memory products. The bond strength is one of the most considerable factors that affect the reliability of such stacked devices. Measurement of wafer-to-wafer bond strength is normally performed by the razor blade method, but there was no such well-established technique for die-to-wafer direct bond. To characterize the die-to-wafer bond strength accurately and conveniently, this work introduced the Schwickerath three-point bending test and derived an analytical solution of bond energy, which does not require initial crack preparation. To examine the correctness of applying this method in a novel area, finite element method (FEM) and razor blade experiments on equivalent samples were conducted. Furthermore, the annealing effect on die-to-wafer bond strength was studied. Top die thickness, loading rate in three-point bending test, and the compensation factor of analytical solution are discussed and summarized in this study.

Solder reflow technology is volume manufacturing ready. Unfortunately, it appears to be limited to a minimum pitch of 40 µm. Therefore, the industry is searching for a solid-state bonding technology to enable further pitch scaling. The candidate technology should have the following key attributes: 1) a mechanism to precisely control the metal height variation to prevent open joints, 2) high-assembly throughput, 3) low-temperature for certain applications, and 4) a pathway to future generations of chip scaling. Direct Bond Interconnect (DBI®) technology achieves all attributes listed above.

This paper presents bonding and electrical yield results with a test vehicle design that demonstrates high-density, fine pitch bonding with high-yield. The test vehicle consists of daisy chain test patterns with 4 μm bonding pitch with 115k links and covers a bond area of 3.61 mm ² . The process flow enables high throughput processing with room temperature bonding and post-bond batch anneal. The process shows minimum electrical yield greater than 98% across all wafers. Longer chains of 500k links with a 3 μm diameter pad with a 10 μm pitch show similar yields. Temperature cycling and autoclave tests of the 3 μm diameter pad test structures showed a robust Cu-Cu interconnection and superior reliability performance.